Integrated circuits (ICs) may be severely damaged by electrostatic discharge (ESD) phenomena. An IC may be exposed to ESD from many sources. A major source of ESD exposure to ICs is the human body. A charge of about 0.6 microcoulombs can be induced on a body capacitance of 100 pF, leading to electrostatic discharge potentials of 4 kV or greater. Any contact by a charged human body with a grounded object, such as a pad of an IC, can produce an electrostatic discharge with approximately a 10 nanosecond (ns) rise time and a discharge time of approximately 450 ns (i.e., the total discharge time is approximately equivalent to three time constants, where each time constant is approximately 150 nanoseconds), during which peak currents of several amps are input into the IC.
A second source of ESD is a metallic object. The metallic object ESD source model is characterized as having a greater capacitance and lower internal resistance than the human body model discussed above. Metallic objects produce ESD transient with approximately the same rise time as a human body discharge but the discharge rings as the nearly negligible resistance of the metallic object results in an underdamped condition.
A third source of ESD is a charge device, involving situations where the IC itself becomes charged and then discharged to ground. The charge device pulses have very fast rise times (approximately one hundred picosecond) compared to those generated by a human body. The charge device current also rings with a short ringing interval of approximately one nanosecond.
A common ESD IC protection scheme uses a network of diodes or transistors and supply clamps to attempt to divert the potentially destructive energy of a static discharge around any sensitive internal circuitry. However, some circuit applications require signal pins of ICs to occasionally operate at voltages above the positive voltage supply (Vdd) or voltages below the negative supply voltage (Vss). The performance of internal circuitry protected by such an ESD protection scheme can become unreliable when signal pins are exposed to required positive or negative pulses that exceed normal operating voltage levels. This is generally due to parasitic currents that occur, through diodes or transistors incorporated in ESD protection schemes, when the voltage levels either exceed Vdd or are lower than Vss. The parasitic currents can degrade the operational signals and cause latch up problems in the ICs.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an ESD protection scheme that is reliable even when required positive or negative voltage signals are applied to signal pins that exceed normal operating voltage levels.